Digital circuits in particular have increased in complexity, density, operating frequency and utility at an astonishing rate over the last several decades. Additionally, increasing functional specialization for integrated circuits has developed as integrated circuit technology has matured. Integrated circuits developed for one set of tasks, such as microprocessors for manipulating digital data, require a first set of process steps. Integrated circuits developed for another set of tasks, such as DRAMs for storing digital data, require a second set of process steps. Integrated circuits developed for a still different set of tasks, such as RF transmitters or receivers for coupling data between devices, require still another set of process steps. The cumulative effect of defects in integrated circuit manufacturing results in a strong preference for using as few processing steps as possible to provide a given integrated circuit function.
For example, if yields for each mask level are 90%, four masking steps result in a total yield of 65%, while six masking steps result in a yield of 53% and eight masking steps result in a yield of 43%. Complex integrated circuits may require several dozen masking steps. Accordingly, there are significant advantages to avoiding exposing a wafer of semiconductor material that will include a microprocessor to masking steps unique to forming DRAMs or RF circuits and vice versa.
As a result, there are economic advantages associated with forming a module or system from an interconnected group of different types of previously-tested integrated circuits (i.e., known good die). Further advantages can result from mounting the different types of integrated circuits in die form on a common substrate and then encapsulating the composite assembly in a package common to all of the die to form a module, known as a multichip module or MCM. In MCMs, the die are interconnected to wiring formed on the common substrate, also known as an interposer, using conventional interconnection technology.
As the area of each die in the MCM increases, thermal coefficient of expansion mismatch between the die and the interposer becomes increasingly critical, at least in part because the thickness of the material forming the die is not increased as the area of the die is increased. One solution to this problem is to make the interposer from the same material that the die are made from, i.e., silicon. This allows increasingly complex integrated circuits to be interconnected without exaggerating thermal coefficient of expansion mismatch problems that could occur either during packaging or as a result of thermal cycling in normal use. Additionally, passive components may be formed or mounted on the interposer, as described in "High Frequency IC to IC Signaling on Rapidly Prototyped Flip Chip MCM-D Substrate", by J. Reed et al., 1998 Int. Conf. on MCMs and High Density Packaging, IEEE Cat. No. 0-7803-4850-8/98, pp. 172-177.
For example, "Integrated Passive Components in MCM-Si Technology and their Applications in RF-Systems," by J. Hartung, 1998 Int. Conf. on MCMs and High Density Packaging, pp. 256-261, IEEE Cat. No. 0-7803-4850-8/98, describes an approach whereby multiple aluminum layers are conventionally formed and patterned on the silicon interposer to provide interconnections. The aluminum layers are separated by conventional Si.sub.3 N.sub.4 interlevel dielectric layers, allowing capacitors to be formed on the silicon interposer. Additionally, a TaSi layer is formed and patterned on the silicon interposer to provide resistors.
However, increasing circuit functionality and the density of components within integrated circuits continue to increase demand for progressively smaller linewidths, both within the integrated circuits themselves and on the interposer. As linewidths shrink, RC transmission line effects in interconnections increase, particularly in longer interconnections. Additionally, these effects are more pronounced as operating frequencies increase. Often, a simple lumped-element model is used to approximate RC effects in long interconnections. Because both the resistance and the capacitance of the interconnection are linearly proportional to the length of the interconnection, signal propagation delays along the interconnection can be modeled as being proportional to the square of the length of the interconnection. Signals traveling along relatively long interconnections suffer delays and other forms of distortion due to frequency-dependent attenuation and cross-coupling between interconnections. As a result, signals transmitted along such interconnections may be corrupted, slowing operation of integrated circuits or even causing failure. "Interconnect Scaling: Signal Integrity and Performance in Future High-Speed CMOS Designs," by D. Sylvester et al., 1998 Int. Conf. on MCMs and High Density Packaging, pp. 42-43, IEEE Cat. No. 0-7803-4850-8/98, discusses signal corruption in transmission of signals within ultra large scale integration CMOS integrated circuits as linewidths shrink and signal propagation distances increase.
Increasing circuit functionality not only increases the density and decreases the width of interconnections, but it also inherently increases the lengths of interconnections as die sizes increase to accommodate the increased functionality. Increased interconnection lengths further exacerbate the above-described problems.
There is therefore a need for improved interconnection technology in MCMs in order to be able to provide MCMs that can accommodate both higher operating frequencies and greater interconnection densities.